MOHITE
MOHITE
Rohith Mohite
I design the analog blocks where physics becomes a system — right now, high-speed data converters in silicon.
From a single transistor to a working system.
I'm an electronics engineer from Bangalore, wrapping up my BE in Electronics & Communication at MSRIT (GPA 8.81) and heading to Politecnico di Milano this September for an MSc in Electrical Engineering.
My home is analog and mixed-signal IC design. I like the part of the craft where intuition, hand calculation and the simulator all have to agree — sizing a transistor with gm/Id until a whole converter behaves the way the math promised.
Beyond the bench I lead — as ECE student representative and placement coordinator, and on donation and blood-camp drives with the Broseph Foundation and NSS.
Tools of the trade.
- Electronic–photonic integration — driver amps & TIA chains at the CMOS–photonics interface
- Full SAR ADC tapeout on GF 22nm FD-SOI
- In-memory computing & SRAM-based accelerators for CNNs
What's on the bench now.
High-Speed SAR ADC
12-bit · 400 MSpsProject lead on a 12-bit, 400 MSps SAR ADC in GPDK 90nm. Currently designing the dynamic comparator — a three-stage cascaded preamplifier into a StrongArm regenerative latch, targeting ~260 V/V gain in 117 ps to resolve a 48.8 µV (½-LSB) input. Sized via gm/Id lookup tables across SS/NN/FF corners; the block seeds a full ADC on GF 22nm FD-SOI with RFIC Technologies.
gm/Id Sizing Toolkit
PyQt6 · desktopA standalone Windows app that automates the gm/Id lookup-and-sizing workflow — point lookup, gds/Id filter, W calculator, sheet viewer and a persistent comparison stack — driven by ~35 SPICE-characterised tables (L = 100 nm – 1 µm, all corners).
Analog IC Design Intern
RFIC TechnologiesCollaborating on a 12-bit SAR ADC on the GF 22nm FD-SOI PDK for transceiver applications.
Things I've already shipped.
32-bit Carry Look-Ahead Adder
Verilog HDL, synthesis & timing analysis — meaningfully faster than ripple-carry.
UVM ALU Verification
Modular testbench — agents, driver, self-checking scoreboard, constrained-random coverage.
GNSS-Denied Indoor Nav
Team lead, 4 people. LiDAR + RSSI localization; campus pilot, commissioned by MSRIT.
Zosh Aerospace Intern
STM32L433 avionics firmware; verified 1000+-pin burn-in PCBs; hardware-in-the-loop testing.
VLSI Circuits & Systems — Project-Based Learning
MOS device physics through neuromorphic architectures — in-memory computing for CNNs, SRAM accelerators, low-power Verilog.
The roadmap.
Tape out the SAR ADC comparator, then the full converter — and ship the two papers in preparation.
MSc at Politecnico di Milano — go deep on data converters and analog front-ends for communication systems.
Work at the CMOS–photonics interface — driver amplifiers and TIA chains for high-bandwidth optical links.
Keep leading and giving back — the donation drives, the mentoring, the people part of engineering.
How I got here.
The part's packaged.
Let's talk.
Open to research collaborations, internships and conversations about analog/mixed-signal design — or anything silicon. Reach out.
